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[Channel Lab]
S5H1420
[Channel Decoder for DVB-S/DSS]
DATA SHEET
Samsung Electronics Co, Ltd.
10 Jan. 2004 (Version 4.5.1)
Note: This documentation is preliminary and is subject to change. Samsung Electronics Co, Ltd. reserves the right to do any kind of modification in this data sheet regarding hardware or software implementations without notice.
Samsung Electronics Co, Ltd. Proprietary Information
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S5H1420
DBS Channel Decoder for DVB-S/DSS
TABLE OF CONTENTS page 1. INTRODUCTION...................................................................................................3 1.1 Overview ..............................................................................................................3 1.2 Features.................................................................................................................3 1.3 Applications............................................................................................................3 1.4 Ordering Information...................................................................................................3 1.5 Functional bock diagram ...........................................................................................4 2. IN INFORMATION...................................................................................................4 2.1 Pin assignment.........................................................................................................4 2.2 Pin description.........................................................................................................5 3. FUNCTIONAL DESCRIPTION ..........................................................................................6 3.1 Signal processing ...................................................................................................6 3.1.1 I & Q inputs ................................................................................................6 3.1.2 PRE - AGC......................................................................................................6 3.1.3 Root raised cosine and rate conversion filter .........................................................6 3.1.3 Offset cancellation ..............................................................................................6 3.1.4 POST - AGC .....................................................................................................6 3.2 Timing recovery......................................................................................................6 3.2.1 Timing control...................................................................................................6 3.2.2 Loop equation................................................................................................. 7 3.2.3 Timing lock indicator... ........................................................................................7 3.3 Carrier recovery and derotator loop ............................................................................7 3.3.1 Loop equation ................................................................................................7 3.3.2 Carrier lock detector...........................................................................................8 3.3.3 Derotator frequency............................................................................................8 3.3.4 Automatic frequency detector...............................................................................8 3.3.5 False lock.........................................................................................................8 3.4 Forward error correction..........................................................................................8 3.4.1 FEC modes.....................................................................................................8 3.4.2 Soft decision...................................................................................................8 3.4.3 Viterbi decoder and synchronization.....................................................................8 3.4.4 Synchronization................................................................................................9 3.4.5 Error monitoring...............................................................................................9 3.4.6 Convolutional deinterleaver.................................................................................9 3.4.7 Reed-Solomon decoder and descramble...............................................................9 3.4.8 Spectrum Inverse of Code Rate 5/6.......................................................................10 3.4.9 MPEG interface................................................................................................10 3.4.9.1 Parallel output interface..............................................................................10 3.4.9.2 Serial output interface.................................................................................10 3.4.9.3 MPEG Clock Control .................................................................................12 3.5 Front end interface.......................................................................................13 3.5.1 I2C interface....................................................................................................13 3.5.2 Write operation (Normal Mode)...........................................................................13 3.5.3 Read operation (Normal Mode)...........................................................................13 3.5.4 Identification register.........................................................................................13 3.5.5 Sampling frequency..........................................................................................13 3.5.6 Clock generation..............................................................................................13 3.5.7 I2C Bus repeater...............................................................................................14 3.5.8 DiSEqC interface.............................................................................................14 4. REGISTER LIST...........................................................................................................16 5. ELECTRICAL CHARACTERISTICS.................................................................................26 5.1 Absolute maximum ratings........................................................................................26 5.2 Recommended operating conditions...........................................................................26 5.3 DC electrical characteristics......................................................................................26 5.4 A/D converter.........................................................................................................26 5.5 Timing characteristics..............................................................................................27 5.6 I2C Bus characteristics.............................................................................................28 6. APPLICATION EXAMPLES............................................................................................29 6.1 Application examples with DVB-S Tuner.....................................................................29 7. PACKAGE DIMENSION.................................................................................................30 8. Data Sheet Update History..............................................................................................31
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S5H1420
DBS Channel Decoder for DVB-S/DSS
1. INTRODUCTION
1.1 Overview The S5H1420 is a single chip channel decoder IC for DBS (Digital Broadcasting System for Satellite) receiver. It consists of a multi-standard QPSK/BPSK demodulator and FEC (Forward Error Correction) decoder compliant with DVB-S and DSS standard. For multi-antenna control it provides DiSEqC1.x and 2.0 standards. 1.2 Features Compliant to DVB-S and DSS standard. Single chip decoder (ADC/QPSK/FEC). Flexible Interface (I2C, MPEG2). DiSEqC 1.x or 2.0 specification support. Satellite dish control. DC offset cancellation. Automatic gain control Nyquist filter: 0.35 for DVB-S, 0.2 for DSS. Fully digital synchronization. Symbol timing recovery range up to 50000 ppm. Carrier recovery range up to 12.5% of symbol rate. Carrier offset cancellation up to 1/2sampling frequency Modulation rate from 1 to 87Mbps(1 ~ 50 Msps) QPSK demodulation quality estimation Viterbi decoding quality estimation. Viterbi Input and output BER measurement. Support depuncturing code rate from 1/2 to 7/8. Convolutional deinterleaver and Reed-Solomon decoder Automatic byte and frame synchronization Automatic spectral inversion ambiguity resolution. I2C repeater for RF part Power down control Low power CMOS technology 3.3V Single power using diode for 2.5V Compact size package: 64LQFP-1010
1.3 Applications DVB-S Receiver and STB Digital satellite TV PCI satellite Card
1.4 Ordering information Type Number 1. S5H1420X01
Package 64 LQFP-1010
Description Plastic Low Profile Quad Flat Package; 64 leads (lead length 1.0mm) Body 10x10x1.0 mm
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S5H1420
DBS Channel Decoder for DVB-S/DSS
1.5 Functional bock diagram
Dual ADC Phase Rotator Digital Filter
AGC
Timing Phase Recovery
Viterbi Decoder
Byte Sync
Deinterleaver
Lock Indicator
Error Monitor
RS Decoder
I2C I/F
Clock Generator
DiSEqC I/F
MPEG I/F
Descrambler
2. PIN INFORMATION 2.1 Pin Assignment
Figure1: Pin-out for 64-pin LQFP
FMHZCLKOUT ADC_OSC_IN AVDD_ADC XTAL_OUT AVDD_PLL 34 AVBB_PLL 33 32 31 30 29 28 27 AVSS_PLL AVDD_PLL DATA7 TEST_SEL1 TEST_SEL0 VDD25 VSS25 ID_SEL1 ID_SEL0 CLK_SEL SCL SDA VDD25 VSS25 NC DATA6 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DATA5 AVSS_PLL 35 VDD33
48 AVSS_ADC QN QP AVBB_ADC VREF_L VREF_H CML AVSS_ADC AVDD_ADC VSS25 VDD25 AGC DiSEqC BYTE_CLK VSEL LNB_EN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
47
46
45
44
43
42
41
40
39
38
37
36
S5H1420
64-LQFP Top View
RESET_N
ERROR
DATA0
DATA1
DATA2
DATA3
XATL_IN
RFSDA
RFSCL
VDD25
VDD33
VSS25
VSS33
IN
IP
DATA4
VDD25
VSS25
VSS33
VALID
SYNC
OLF
NC
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S5H1420
DBS Channel Decoder for DVB-S/DSS
2.2 Pin descriptions
Pin Name OLF RESET_N ERROR SYNC VALID NC DATA DATA I/O Cell Type Input Schmitt Trigger Error_out Sync_out Valid_out NC Output [7] Output [7:0] Pin Number 1 2 3 4 5 6 30 [:] 21 22 23 24 24 28 29 18 36 37 38 41 42 45 46 47 48 50 51 53 54 55 60 61 62 63 64 46, 57 56, 49 52 31 32 33 34 35 13, 39 14, 40 7, 19, 26, 43, 58 8, 20, 27, 44, 59 Description LNB Over Load Flag H/W Reset (Active Low) Error indicator output Synchronization output Valid data period NC MPEG2 Stream Serial Data MPEG2 Stream Parallel Data [Pin 30,17,16,15,12,11,10,9] Serial Data from host Serial Clock from host Master Clock Select I2C Address Select[T0] I2C Address Select[T1] Test Mode Select[T2] Test Mode Select[T3] No connection Crystal Oscillator Input Crystal Oscillator Output Reference Clock Output RF Module Control SDA RF Module Control SCL Oscillator Input ADC Total Power ADC Analog Input ADC Analog Input ADC Analog Input ADC Analog Input ADC Bottom Reference Voltage ADC Top Reference Voltage Common Mode Level Voltage Gain Control Output Antenna Select Data Transfer clock LNB Voltage Select Flag LNB Enable Flag
SDA I/O-open drain(5V) SCL Input(5V) CLK_SEL Input ID_SEL0 Input ID_SEL1 Input TEST_SEL0 Input TEST_SEL1 Input NC NC XTAL_IN Oscillator Input XTAL_OUT Oscillator Output FMHZCLKOUT Output RFSDA I/O-open drain (5V) RFSCL n-ch-open drain (5V) ADC_OSC_IN Oscillator Input AVDD_ADC Digital Power IP Inphase Positive IN Inphase Negative QN Quadrature Negative QP Quadrature Positive VREF_L Analog Reference VREF_H Analog Reference CML Analog Reference AGC n-ch Open Drain(5V) DISEQC Bidirectional (5V) BYTE_CLOCK Output (3.3V) VSEL Output LNB_EN Output RF Interface & ADC Power Supply (24) ADC AVDD_ADC AVSS_ADC AVBB_ADC AVDD_PLL AVSS_PLL AVBB_PLL AVDD_PLL AVSS_PLL VSS33 VDD33 VSS25 VDD25
PLL
IO Logic
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S5H1420
DBS Channel Decoder for DVB-S/DSS
3. FUNCTIONAL DESCRIPTION
3.1 Signal processing 3.1.1 I and Q inputs The dual ADC can get differential (IP/IN, QP/QN) or single inputs (IP, QP), I/Q signals from the tuner are fed to the IP and QP inputs through a DC coupling capacitor and IN and QN must be set DC voltage as CML (typical: 1/2VDD). The reference voltage of high [VREF-H] and low [VREF-L] should be supplied from external generator for application flexibility. 3.1.2 PRE-AGC The power of I/Q signal is compared to a programmable threshold value, and the difference is integrated. This signal is then converted into a Pulse Width Modulation (PWM) signal to drive the AGC output and it will be low pass filtered by a simple RC analog filter to control the gain command of any amplifier before the A/D converter. The PWM output operates at fclk/ (1, 4, 8 and 16) in order to decrease the radiated noise and to simplify the filter design, and is a 5 V tolerant open drain stage. The PRE-AGC Controls are in Address 0x07 and the PRE-AGC integrator register is in Address 0x15. 3.1.3 Root raised cosine and rate conversion filter The Root raised cosine (RRC) and rate conversion filter performs anti-aliasing filtering, root raised cosine shaping, rate conversion, timing synchronization and tracking with the timing loop. Two roll-off factors are available: 0.35 (DVB-S) and 0.20 (DSS). 3.1.4 Offset cancellation This device suppresses the residual I/Q DC component in the QPSK system control register in Addresses 0x05 and 0x06. 3.1.5 POST-AGC The POST-AGC shall be able to adjust the gain of the incoming I/Q sample from the RRC and rate conversion filter and implement the closed loop that sets the gain adjustment. The reset value (0x8000) of the POST-AGC integrator register can allow an initial settling time of less than 50k master clock periods. The POST-AGC Controls are in Address 0x08 and the POST-AGC integrator register is in Address 0x16.
3.2 Timing recovery 3.2.1 Timing control The timing loop is programmed with the expected symbol frequency. We have parameter, which determine one or two sampling method. It can be expressed as: (1+ ) In contrast, (1+ ) fsym < f clk for =2. 2 fsym > f clk for =1. 2
Where is roll-off factor: 0.35 for DVB-S, 0.2 for DSS. Thus Timing NCO frequency word register setting is: NCO frequency word =
f sym f clk
224
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S5H1420
DBS Channel Decoder for DVB-S/DSS
3.2.2 Loop equation The timing loop may be considered as a second order loop. The loop equation may be calculated using the following formula: = 1<< ((Pg+8) - Ig)
= t (1<< Ig)
Where, Pg is propagational gain, Ig is integral gain and t is timing factor. t = 5.0
x
1
And we can choose Loop
2 24 f sym f clk
Bandwidth (BL), as follows:
1 1 BL = x x x (1 + 2 ) 2 4
Where is the reference level of the
and
.
=
x
2
3.2.3 Timing lock indicator The timing detector need to a lot of symbols for stabilization in order to lock after tuning frequency change of RF and it takes a 1-bit input signal, and uses the presence or absence of locking information to either count up or count down respectively. The counter operates up to reaches its maximum value when the lock signal goes active. Two cases can cause the lock signal to go to unlocked state; one is assertion of the active-low reset and the other the counter go zero again. User can monitor the MSB 8 bits of TLL (timing lock loop) counter in Address 0x1a and the TLL lock flag in Address 0x14. 3.3 Carrier recovery The tracking range of the derotator is fclk /2 ( fsampling/2). This algorithm is used with QPSK reception, over a small range of capture phases and with a channel noise value over 3.0 dB. 3.3.1 Loop equation Like the timing loop, the carrier loop is a second-order system where two parameters, and . = 1<< ((Pg+8) - Ig)
= p (1<< Ig)
Where, Pg is propagational gain, Ig is integral gain and p is phase factor.
p = 75.4
x
2 f sym f clk
1 24
Also, we can choose Loop Bandwidth (BL), as follows:
1 1 BL = x x x (1 + 2 ) 2 4
Where is the reference level of the
and
.
=
x
2
3.3.2 Carrier lock detector
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S5H1420
DBS Channel Decoder for DVB-S/DSS
The carrier lock detector operates the same as the timing lock detector in the Phase locked loop (PLL). User can monitor the MSB 8 bits of PLL lock counter in Address 0x19 and the PLL lock flag in Address 0x14. 3.3.3 Derotator frequency The derotator frequency can be either measured (read operation) or forced (write operation).
f sym x 2 fderot = f clk
24
3.3.4 Automatic frequency detector The automatic frequency detector (AFD) can evaluate the carrier frequency offset quickly, and may be coupled to the carrier recovery loop. The digital loop filter of PLL has two paths, proportional and integral, with programmable gain respectively. The integral path contains an accumulator whose contents can be analyzed as a averaged carrier frequency offset. The phase error signal goes into two paths, the respective gains are applied, the "I" path is integrated, and the two are added together. A Kicker of AFD can help PLL to achieve lock fast. The Kicker finds the phase error signal for large transitions, inserts a large value, into the "I" path. Therefore, PLL can trace the large frequency offset. 3.3.5 False lock A false lock occurs when phase lock has been detected in the QPSK, but the correct central frequency has not yet been reached. This situation occurs in QPSK for frequency offset points that are multiples of fsym /4, where fsym is the QPSK symbol rate, and also at other offsets dictated by the discrete nature of the carrier recovery loop. Therefore, the carrier recovery loop must be handled to take care of a false lock condition.
3.4 Forward Error Correction 3.4.1 FEC modes Since the S5H1420 is a multi-standard decoder, several combinations are possible, at different levels: the demodulator may accept either QPSK or BPSK signals - the only impact is on the carrier algorithm choice. The algorithm choice also affects the carrier lock detector and the noise evaluation. there are two primary options concerning the FEC operation - between DVB-S, DSS and Reserved Mode. there are two options concerning the FEC feeding. The first is IQ flow, which is the usual case in QPSK modes DVB-S or DSS. The second mode is I-only flow, used for BPSK. The FEC Mode Register is in Address Hex 22. In Modes DVB-S and DSS, data is fed to the Soft Decisions. 3.4.2 Soft decisions The adaptive equalizer output is converted into 4-bit sign-magnitude format by the soft decision block, for use by the Viterbi decoder. The MSB corresponds to the sliced bit value. The 3 LSBs of the soft decisions represent the confidence of the sliced bit value, where 111 are high confidence, and 000 is low confidence. A programmable set of thresholds can be used in generating the three LSBs and, consequently, in optimizing the Viterbi decoder performance as a function of code rate. 3.4.3 Viterbi decoder and synchronization The convolutional codes are generated by the polynomial Gx = 171 octets and Gy = 133 octets in modes DVB-S or DSS. The Viterbi decoder computes for each symbol the metrics of the four possible paths, proportional to the square of the Euclidian distance between the received I and Q and the theoretical symbol value. The puncture rate and phase are estimated on the error rate basis. Several rates are allowed and may be enabled/disabled through register programming: -8 Samsung Electronics Co, Ltd. Proprietary Information
S5H1420
DBS Channel Decoder for DVB-S/DSS
1/2, 2/3, 3/4, 5/6, 7/8 for DVB-S 1/2, 2/3, 6/7 for DSS For each enabled rate, the current error rate is compared to a programmable threshold. If it is greater than this threshold, another phase (or another rate) is tried until the right rate is obtained. A programmable hysterics is added to avoid losing the phase during short-term perturbation. The rate may also be imposed by external software, and the phase is incremented only upon request by the microprocessor. The error rate may be read at any time in order to use an algorithm other than that implemented. The Viterbi decoder produces an absolute decoding. The decoder is controlled via several Viterbi Threshold Registers (Registers 29, 2A, 2B, 2C, 2D and 2E). For each Viterbi Threshold Register, bits 7 to 0 represent a normalization rate threshold - the average number of normalization occurring during sync periods. The sync period is controlled via Viterbi Sync Register (Register 2F). The puncture Rate and Viterbi initial configuration is in Address 30, 31. The automatic rate research is only done through the enabled rates (see the corresponding bit set in the Puncture register). In DSS, it is recommended that you disable puncture rates 3/4, 5/6 and 7/8 in order to save time in the synchronization process. The Viterbi decoder sync search can control using the Puncture register. 3.4.4 Synchronization In DVB-S, the packet length after inner decoding is 204. The sync word is the first byte of each packet. Its value is Hex 47, but this value is complemented every 8 packets. In DSS, the packet length is 147 and the sync word is Hex 1D. An Up/Down Sync counter counts whenever a sync word is recognized with the correct timing and counts down during each missing sync word. This counter is bounded by a programmable maximum - when this value is reached, the SYNC_FLAG bit ("locked") is set in the SYNC02 register. When the event counter counts down to until 0, this flag is reset. 3.4.5 Error monitoring A 16-bit counter, ERRCNT, allows the counting of errors at different levels. ERRCNT is fed either by: the input QPSK bit errors (that are corrected by the Viterbi decoder), or, the bit, or, the byte error (it will be corrected by the Reed-Solomon decoder) the packet error (It is uncorrectable and lead to a pulse at the ERROR output) The content of ERRCNT may be transferred to the read only registers ERR_CNT_L (LSB) and ERRCNT_H (MSB). Two functional modes are proposed, depending on a control register bit: 1. ERR_DISP = 0. The uncorrectable block flag ERROR that error count is not incremented. 2. ERR_DISP = 1. The uncorrectable block flag ERROR that error is counted as 27 erroneous bits (It has nine erroneous bytes with three corrupted bits per byte). 3.4.6 Convolutional deinterleaver In DVB-S, the Convolutional deinterleaver is 17 12. The periodicity of 204 bytes per sync byte is retained. In DSS, the Convolutional deinterleaver is 146 13, and there is also a periodicity of 147 bytes per sync byte. The deinterleaver may be bypassed.
x
x
3.4.7 Reed-Solomon decoder and descrambler The input blocks are 204-byte long with 16 parity bytes in DVB-S. The sync byte is the first byte of the block. Up to 8 byte errors may be fixed. The code generator polynomial is: g( ) = ( - 0) ( - 1) (...) ( - 15) Over the Galois Field generated by: 8 + 4 + 3 + 2 + 1=0 Energy dispersal descrambler and output energy dispersal descrambler generator: 15 + 14 + 1 The polynomial is initialized every eight blocks with the sequence 100101010000000. The sync words are unscrambled and the scrambler is reset every 8 packets. -9 Samsung Electronics Co, Ltd. Proprietary Information
S5H1420
DBS Channel Decoder for DVB-S/DSS
The output interface may be forced into high impedance mode by setting MPEG_OEN =0 in the Address 39. Doing this affects the DATA [7:0], BYTE_CLOCK, SYNC, VALID and ERROR pins. The output stream is either parallel (byte stream) or serial (bit stream) depending on bit 1 of Address 39. 3.4.8 Spectrum Inverse of Code Rate 5/6 In case of Code Rate 5/6, because of its character, regardless of condition of spectrum it can be locked. Rest of the code rates except 5/6, if Viterbi is locked, byte becomes sync but in case of code rate 5/6, even if Viterbi is locked there are chances byte does not become sync. Therefore, in case of Code Rate 5/6, it should be processed using S/W. Processing procedure is like below. 1. When the rest is locked except byte sync, code rate check 5/6. - Code rate monitoring : Addr [0x32], Bit position[0-2] 2. When Code Rate is 5/6, Check inverse spectrum status. - Spectrum inverse monitoring : Addr [0x32], Bit poisition[3] 3. Inverse inversion spectrum. - Spectrum inverse setting : Addr [0x31], Bit poisition[3], Set 1 Addr [0x31], Bit poisition[4], Set 1 or 0 3.4.9.1 Parallel output interface A schematic diagram of the parallel output interface is shown in Figure 4. The parallel output format is compliant with the DVB-S common interface protocol. When the byte sync is not found (SYNC_FLAG = 0 in the SYNC02 register), VALID (corresponding to the MiVAL signal of the DVB-S common interface standard) remains at a low level. BYTE_CLOCK has a duty cycle between 40 and 60%. The VALID signal is generated depending on bit 2 of Address 39. The BYTE_CLOCK, SYNC, VALID and ERROR signal polarity is controlled depending on contents in the Register 38. 3.4.9.2 Serial output interface The serial output interface is shown in Figure5. The serial bit stream is available on D7, where MSB is first to reconstruct the original order. If MPEG_DOUT = 1, then the parity bits are output (Register 39). If MPEG_DOUT =0, the data is null during the parity time slots. SYNC is only high during the first bit of each packet, instead of during the first byte in Parallel mode. ERROR has the same function as in parallel mode. BYTE_CLOCK is the serial bit clock; it is same the master clock, fclk. All of the outputs are synchronous of the same master clock edge. D7, SYNC, VALID and ERROR may be properly sampled externally by the rising edge of BYTE_CLOCK. The first bit detected in a valid packet may be decoded if it is found on the appropriate edge of BYTE_CLOCK, where SYNC = 1, ERROR = 0, VALID = 1. The following bits only require the assertion of VALID (while VALID = 1,). Outputs D0 to D6 remain at low level in serial mode.
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S5H1420
DBS Channel Decoder for DVB-S/DSS
Figure4 : Parallel output interface
No Error Data MPEG_CLK=1 CDCLK_POL=1 MPEG_CLK=0 BYTE_CLOCK MPEG_CLK=1 CDCLK_POL=0 MPEG_CLK=0 VALID SYNC Parity Uncorrectible Packet No Error
MPEG_ERR=1 ERROR MPEG_ERR=0
Figure5 : Serial output interface
SYNC 1/fclk CDCLK_POL=1 BYTE_CLOCK CDCLK_POL=0 DATA VALID MPEG_DOUT=1 D0 MPEG_DOUT=0 MPEG_ERR=1 ERROR MPEG_ERR=0 1 packet First bit of the packet Useful Data Parity Parity
Table 0 Bit1 of 0x39 SER_PAR 0 1 Bit4 of 0x02 SER_SEL_MODE 1 1 MPEG Data DATA [7:0] DATA[7] MPEG Clock BYTE_CLK BYTE_CLK
Parallel Serial
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S5H1420
DBS Channel Decoder for DVB-S/DSS
3.4.9.3 MPEG Clock Control - Through Register Setting, S5H1420 can control MPEG CLOCK to MCU. STB MCU Symbol Rate S5H1420 Master Clock Sampling 60MHz Symbol Rate Symbol Rate >= 25 < 25 59MHz 1 88MHz 2 81MHz Symbol Rate Symbol Rate >= 25 < 25 80MHz 1 88MHz 2
- Control register, 3-bit, uses Address 0x22 (MPEG_CLK_INTL [2:0]) - If Control registers changes, Some blocks will be reset automatically. - In case, Auto reset does not work, these blocks' reset can be done manually. - MPEC IF Clock is made by Control Register and the Rules are as follows - Tmp = (fMCLK/fSR)*(1/(2*CR)), fMCLK : System Clock Frequency,fSR : Symbol Rate, CR : Code Rate MCLK=88 MHz MPEG Clock (MHz) Serial 1Control Register (0x22) 0 1 2 3 4 5 6 7
MPEG Clock(Parallel) FMCLK/8 FMCLK/16 FMCLK/32 FMCLK/64 FMCLK/96 FMCLK/128 FMCLK/192 FMCLK/256
MPEG Clock (Serial) FMCLK FMCLK/2 FMCLK/4 FMCLK/8 FMCLK/12 FMCLK/16 FMCLK/24 FMCLK/32
Range
Divide
Example1) System Clock Frequency = 88MHZ, Symbol Rate : 44MSps Code Rate 1/2 2/3 3/4 5/6 6/7 7/8 Tmp Value 2 1.5 1.333 1.2 1.166 1.142 Setting Control Register Value 1 0 0 0 0 0
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S5H1420
DBS Channel Decoder for DVB-S/DSS
3.5 Front end interfaces 3.5.1 I2C interface The standard I2C protocol is used whereby the first byte is Hex A0 for a write operation, or Hex A1 for a read operation. 3.5.2 Write operation The byte sequence is as follows: the first byte gives the device Address plus the direction bit (R/W = 0). the second byte contains the internal Address of the first register to be accessed. the next byte is written in the internal register. Following bytes (if any) are written in successive internal registers. the transfer lasts until stop conditions are encountered. the S5H1420 acknowledges every byte transfer. 3.5.3 Read operation The Address of the first register to read is programmed in a write operation without data, and terminated by the stop condition. Then, another start is followed by the device Address and R/W= 1. All following bytes are now data to be read at successive positions starting from the initial Address. Figure 2 shows the I2C Normal Mode Write and Read Registers. Figure 2: I2C Read and Write operations in Mode Write register 0 to 3 with AA, BB, CC, and DD
Read register 2 and 3
3.5.4 Identification register The Identification Register (at Address Hex 00) gives the release number of the circuit. The content of this register at reset is presently (Hex02) 3.5.5 Sampling frequency The S5H1420 converts the analog inputs into digital 6 bit I and Q flow. The sampling frequency is fclk which is derived from an external reference described in Section 3.5.6 `Clock generation'. The maximum value of fclk is 90 MHz. The sampling causes the repetition of the input spectrum at each integer multiple of fclk One has to ensure that no frequency component is folded in the useful signal bandwidth of fsym (1+ )/2 where fsym is the symbol frequency, and is the roll-off value. 3.5.6 Clock generation An integrated PLL is the circuit synchronizing an output signal (generated by a VCO with a reference signal in frequency as well as in phase. In this application, it includes the following basic blocks. The phase frequency detector to detect the phase difference between the reference frequency and the output frequency (after division) and to control the charge pumps voltage. Register setting can program the desired frequency. fout = (m fin)/ (p s) fin: input frequency, m=M+8, p=P+2, s=2^S M: Register 03, P: Register 04 [5:0], S: Register 04[7:6]
x
x
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S5H1420
DBS Channel Decoder for DVB-S/DSS
3.5.7 I2C bus repeater In low symbol rate applications, signal pollution generated by the SDA/SCL lines of the I2C bus may dramatically worsen tuner phase noise. In order to avoid this problem, the S5H1420 offers an I2C bus repeater so that the RFSDA and RFSCL are active only when necessary. Both RFSDA and RFSCL pins are set high at reset. When the microprocessor writes a 1 into register bit I2C_RPT, the next I2C message on SDA and SCL is repeated on the RFSDA and RFSCL pins respectively, until stop conditions are detected. To write to the tuner, the external microprocessor must, for each tuner message, perform the following: Program 1 in I2C_RPT. Send the message to the tuner. Any size of byte transfers is allowed, regardless of the Address, until the stop conditions are detected. Transfers are fully bi-directional. The I2C_RPT bit is automatically reset at the stop condition. The I2C repeater register in Address Hex 02 controls configuration. 3.5.9 DiSEqC interface This interface allows for the simplification of real time processing of the dialog from microprocessor to LNB. It includes register set (8 bytes) that is filled by the microprocessor via the I2C bus, and then transmitted by modulating to 22 kHz clock. The S5H1420 support DiSEqC2.0 for bi-directional interface between microprocessor to LNB and can change the tone frequency by register setting. < Transmission > The S5H1420 have three modes for DiSEqC Interface. Continuous Mode: The S5H1420 generates continuous tone signal until the mode changes. Tone Burst Mode: For the "Modulated Tone Burst", only one byte (with value Hex FF) and parity bit 1 is sent. As a result, the output signal is 9 bursts of 0.5ms, separated by 8 intervals of 1ms. For the "Unmodulated Tone Burst" only one byte (with value Hex 00) is sent. The parity bit is still 1, and as a result, the signal is a continuous train of 12.5ms. DiSEqC Mode: DiSEqC is a command-based protocol used to control multiple LNBs in a cascaded network configuration. The S5H1420 complies with DiSEqC2.0. Figure illustrates a typical application of the DiSEqC mode. < Receive > The S5H1420 receives the data from LNBs using DiSEqC pin. In order to receive the data from LNBs should set the register RCV_EN to 1. The received data is stored to register set. Two control signals are available on the I2C bus: DiS_RDY (Transfer Ready/Finish) and DiS_LENGTH (Message Length). A typical byte transfer loop, as seen from the microprocessor, may be the following: While (there is data to transfer) 1 Read the DiS_RDY signals 2 If DiS_RDY =0, Write byte to transfer in the register set. 3 Set the DiS_LENGTH. 4 Set the DiS_RDY =1. Note, for the above transfer loop, the following: At the beginning, the register set is empty (DiS_RDY =0). This is the idle state. As soon as set the DiS_RDY =1, the transfer will begin. After the last transmitted byte, the interface will go into the idle state.
- 14 Samsung Electronics Co, Ltd. Proprietary Information
S5H1420
DBS Channel Decoder for DVB-S/DSS
Figure3: Schematic showing Bit Transmission
Idle 11 Periods 11 Periods 11 Periods Next bit
Transmission of 1's
Transmission of 0's
b)SWITCH_CON=0
SWITCH_CON Register set Output X Empty Continuous tone 0 DATA=00 Unmodulated tone burst 01 1 DATA=FFor00 Module tone burst 10 x Note 1 DiSEpC signal 11 x xx Reserved Note: 1 Byte to transfer in DiSEqC mode. 2 In Mode LNB_CON (1:0) =10, the DiSEqC pin return to high 2 mode once the transmission is completed.
Table1 LNB_CON 00
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S5H1420
DBS Channel Decoder for DVB-S/DSS
4. REGISTER LIST
Add ID SYSTEM PLL 0x00 0x01 0x02 0x03 0x04 0X05 0X06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0X10 0X11 0X12 0X13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1F 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0X2A 0X2B 0X2C 0X2D 0X2E 0X2F 0X30 0X31 0x32 0x33 0x34 0x35 0x36 0X37 0X38 0X39 0X3A 0X3B 0X3C 0X3D 0X3E 0X3F 0X40 0X41 0X42 0X43 0X44 0x45 0X46 0x47 0x48 0x49 Name ID01 CON_0 CON_1 PLL01 PLL02 QPSK01 QPSK02 Pre01 Post01 Loop01 Loop02 Loop03 Loop04 Loop05 Pnco01 Pnco02 Pnco03 Tnco01 Tnco02 Tnco03 Monitor01 Monitor02 Monitor03 Monitor04 Monitor05 Monitor06 Monitor07 Monitor12 FEC01 Soft01 Soft02 Soft03 Soft04 Soft05 Soft06 Vit01 Vit02 Vit03 Vit04 Vit05 Vit06 Vit07 Vit08 Vit09 Vit10 Vit11 Vit12 Sync01 Sync02 Rs01 Mpeg01 Mpeg02 DiS01 DiS02 DIS03 DiS04 DiS05 DiS06 DiS07 DiS08 DiS09 DiS10 DiS11 Rf01 Err01 Err02 Err03 Err04 0 S KICK_EN 1 INV_PULSE 0 WT_TNCO LOOP_OUT 0 1 0 0 WT_PNCO 1 0 1 DC_EN 1 1 DUMP_ACC 0 bit7 bit6 bit5 bit4 0 SER_SEL bit3 S5H1420_ID SOFT_RST 0 M P 1 MODE DC_WIN Q_START 0 0 0 PWR_DN DSS_DVB I2C_RPT bit2 bit1 bit0
1 KICK_VAL IGA_PLF IGT_PLF IG_TLF
1
0
PRE_TH POST_TH 0 KICK_MUL PGA_PLF PGT_PLF PG_TLF
0
0
QPSK
PNCO0[31:24] PNCO1[23:16] PNCO2[15:08] TNCO0[31:24] TNCO1[23:16] TNCO2[15:08] Reserved TLOCK PLOCK PRE_LEVEL POST_LEVEL DC_I_LEVEL DC_Q_LEVEL Reserved Reserved QPSK_OUT DC_FREEZE 0 0 MPEG_CLK_INTL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved VIT_SR67 VIT_SR56 VIT_SR34 VIT_SR23 VIT_SR12 PARM_FIX INV_SPEC VIT_FR VIT_SPEC_STS VIT_CR
0
0
0
0
VIT_SR78
FEC
SYNC_MISS_TH BYTE_SYNC
SYNC_HIT_TH Reserved ERR_POL CLK_CONT TONE_FREQ DIS_RDY SYNC_POL 1 SWITCH_CON OLF_N VALID_POL SER_PAR VIT_SYNC CDCLK_POL DSS_SYNC
1 RCV_EN
1 DIS_LENGTH
1
LNB_CON LNB_DN V18_13V
LNB_MESGE0 LNB_MESGE1 LNB_MESGE2 LNB_MESGE3 LNB_MESGE4 LNB_MESGE5 LNB_MESGE6 LNB_MESGE7 SLAVE_ADDR ALARM _MODE ERR_CNT_PRD ERR_CNT_L ERR_CNT_H PARITY_ERR
ERR_SRC
- 16 Samsung Electronics Co, Ltd. Proprietary Information
S5H1420
DBS Channel Decoder for DVB-S/DSS
ID control register (Address: 0x00)
Addr. RegName
(Reset val)
Signal name S5H1420_ID
Width Property Description [7:0] R Revision ID
0x00
ID01 (0x03)
System control registers (Address: 0x01-0x02)
Addr. RegName
(Reset val)
Signal name
Width Property Description [4] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Set to "0" System soft reset mode (active high) [1] Enable [0] Disable Set to "0" Set to "0" DSS/DVB mode selection [1] DSS [0] DVB Set to "0" Set to "0" Set to "1" Set to "0" Set to "0" Power down mode
SOFT_RST
[3] [2] [1]
0x01
CON_0 (0x00)
DSS_ DVB
[0] [6] [5]
SER_SEL
[4] [3] [2]
0x02
CON_1 (0x00)
PWR_DN
[1]
R/W
[1] Power down enable [0] Power down disable I2C repeater control [1] I2C repeater enable,
I2C_RPT
[0]
R/W
[0] I2C repeater disable. Note: The master should be set this bit to "1" in order to interface with the tuner. When the master is not communicated with the tuner, this bit should be set to "0"
PLL control registers (Address: 0x03-0x04)
Addr. RegName Signal name 0x03 PLL01 (0x50) PLL02 (0x40) M P S Width Property Description [7:0] [5:0] [7:6] R/W R/W R/W PLL programming information Fout = ((M+8) Fin)/((P+2)x2 ) Fin = 4 MHz
s
0x04
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S5H1420
DBS Channel Decoder for DVB-S/DSS
QPSK control registers (Address: 0x05 - 0x06)
Addr. RegName
(Reset val)
Signal name KICK_EN
Width Property Description [7] [6] [5] R/W R/W R/W R/W R/W R/W R/W [1] PLL Kicker enable [0] Disable Set to "0" Set to "1" DC offset remove [1] Enable [0] Disable Set to "1" Set to "1" QPSK operation mode
DC_EN
[4] [3] [2]
0x05
QPSK01 (0xBC)
MODE
[1]
[1] 1 sampling/1 symbol [0] 2 sampling/1 symbol
Q_START
[0] [7] [6] [5] [4]
R/W R/W R/W R/W R/W
QPSK start signal [1] Start [0] Idle Set to "1" Set to "1" Set to "0" Set to "0" Dump phase loop filter & timing loop
0x06
QPSK02 (0xC1) DUMP_ACC [3] R/W
filter accumulator [0 and then 1] The read operation enabled, when user set DUMP_ACC "0" and then "1".
DC_WIN
[2:0]
R/W
Window position from MSB removing DC offset. Unsigned integer (0 DC_WIN 7)
AGC control registers (Address: 0x07 - 0x08)
Addr. RegName
(Reset val)
Signal name
Width Property Description PWM signal is reversed
INV_PULSE
[7]
R/W
[1] PWM signal active low [0] PWM signal active high
0x07
Pre01 (0x30)
[6] [5] PRE_TH [4:0] [7:6] POST_TH [5:0]
R/W R/W R/W R/W R/W
Set to "0" Set to "1" PRE-AGC threshold Set to "0" POST-AGC threshold
0x08
Post01 (0x10)
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S5H1420
DBS Channel Decoder for DVB-S/DSS
Loop filter control registers (Address: 0x09 - 0x0D)
Addr. RegName
(Reset val)
Signal name WT_TNCO
Width Property Description Write TNCO center frequency [7] R/W [0 and then 1] The write operation enabled, when user set WT_TNCO "0" and then "1" Write PNCO center frequency [0 and then 1] The write operation enabled, when user set WT_PNCO "0" and then "1" Set to "1" Set to "1" Set to "0" Set to "0" Set to "0" Set to "0" Loop filter monitoring selection
WT_PNCO
[6] [5] [4] [3] [2] [1] [0]
R/W R/W R/W R/W R/W R/W R/W
0x09
Loop01 (0x30)
LOOP_OUT
[7]
R/W
[1] Loop filter accumulator + NCO [0] Loop filter accumulator
0x0A
Loop02 (0x65)
KICK_VAL KICK_MUL
[6:4] [3:0] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4]
R/W R/W R/W R/W R/W R/W R/W R/W
The value that gets injected into the accumulator when a "kick" is needed. The number of bits KICK_VAL is up-shifted (2 ) before it is injected into the accumulator. Phase loop, proportional gain (2 (default +8 added) Phase loop, integral gain (2
PGA_PLF N
0x0B
Loop03 (0x78) Loop04 (0x28) Loop05 (0x17)
PGA_PLF IGA_PLF PGT_PLF IGT_PLF PG_TLF IG_TLF
) in the acquisition mode
IGA_PLF
) in the acquisition mode
0x0C
Phase loop, proportional gain in the tracking mode (default +8 added) Integral gain in the tracking mode Timing loop, proportional gain (default +8 added) Timing loop, integral gain
0x0D
NCO control registers (Address: 0x0E - 0x13)
Addr. RegName
(Reset val)
Signal name PNCO1 [31:24]
Width Property Description [7:0] R/W LOOP_OUT [1] Read PLF accumulator + PNCO
0x0E
Pnco01 (0x00) Pnco02 (0x00) Pnco03 (0x00) Tnco01 (0x00) Tnco02 (0x00) Tnco03 (0x00)
0x0F 0x10 0x11 0x12 0x13
PNCO2 [23:16]
[7:0]
R/W
LOOP_OUT [0] Read PLF accumulator
PNCO3 [15:08]
[7:0]
R/W LOOP_OUT [1] Read TLF accumulator + TNCO LOOP_OUT [0] Read TLF accumulator
TNCO1 [31:24]
[7:0]
R/W
TNCO2 [23:16]
[7:0]
R/W
TNCO3 [15:08]
[7:0]
R/W
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S5H1420
DBS Channel Decoder for DVB-S/DSS
QPSK monitoring registers (Address: 0x14 - 0x1F)
Addr. RegName
(Reset val)
Signal name
Width Property Description [7:4] [3:2] R R R Reserved Reserved Timing loop lock (Symbol sync)
Monitor01 0x14 (0x00) TLOCK
[1]
[1] Timing loop has locked [0] Timing loop has not locked Phase loop lock (Carrier sync)
PLOCK
[0]
R
[1] Phase loop has locked [0] Phase loop has not locked
0x15
Monitor02 PRE_LEVEL (0x00) Monitor03 POST_LEVEL (0x00) Monitor04 DC_I_LEVEL (0x00) Monitor05 DC_Q_LEVEL (0x00) Monitor06 (0x00) Monitor07 (0x00) (0x1B ~ 0x1E)
[7:0]
R
PRE-AGC gain level
0x16
[7:0]
R
POST-AGC gain level
0x17
[7:0]
R
DC offset of I samples
0x18
[7:0]
R
DC offset of Q samples
0x19
[7:0]
R
Reserved
0x1A
[7:0]
R
Reserved Reserved
[7]
Reserved R R/W QPSK output monitoring [1] Do not update DC_OFFSET Reserved
0x1F
Monitor12 QPSK_OUT (0x00) DC_FREEZE (0x20 ~ 0x21)
[6:1] [0]
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S5H1420
DBS Channel Decoder for DVB-S/DSS
FEC control registers (Address: 0x22)
Addr. RegName
(Reset val)
Signal name
Width Property Description [6] [5] [4] [3] R/W R/W R/W R/W Set to "0" Set to "0" Set to "0" Set to "0" Tmp=(FMClk/FSR) (1/(2 CR))
0x22
FEC01 (0x01) MPEG_CLK_INTL [2:0] R/W
FMClk: System Clock Frequency FSR: Symbol Rate, CR: Code Rate
0: 12 5 9 13
4: 1317 25 33
Viterbi control registers (Address: 0x30 - 0x31)
Addr. RegName
(Reset val)
Signal name
Width Property Description [7] [6] R/W R/W R/W Set to "0" Set to "0" [1] Include code rate 7/8 in sync search [0] Disable [1] Include code rate 6/7 in sync search [0] Disable [1] Include code rate 5/6 in sync search [0] Disable [1] Include code rate 3/4 in sync search [0] Disable [1] Include code rate 2/3 in sync search [0] Disable [1] Include code rate 1/2 in sync search [0] Disable Parameter fix mode
VIT_SR78
[5]
VIT_SR67 Vit08 (0xFF)
[4]
R/W
0x30
VIT_SR56
[3]
R/W
VIT_SR34
[2]
R/W
VIT_SR23
[1]
R/W
VIT_SR12
[0]
R/W
PARM_FIX
[4]
R/W
[1] Known parameter [0] Unknown parameter
0x31
VIT9 (0x00)
VIT_INV_SPEC
[3]
R/W
Initial spectrum information [1] Inv spectrum [0] Not inv spectrum Start synchronization search at code rate as follows:
VIT_FR
[2:0]
R/W
[0] R=1/2 [1] R=2/3 [2] R=3/4 [3] R=5/6 [4] R=6/7 [5] R=7/8
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S5H1420
DBS Channel Decoder for DVB-S/DSS
Viterbi status registers (Address: 0x32)
Addr. RegName
(Reset val)
Signal name
Width Property Description Spectrum information monitoring
VIT_SPEC_STS
[3]
R
[1] Inv spectrum [0] Not inv spectrum Viterbi decoder current code rate
0x32
VIT10 (0x00) VIT_CR [2:0] R
[0] R=1/2 [1] R=2/3 [2] R=3/4 [3] R=5/6 [4] R=6/7 [5] R=7/8
SYNC control register (Address: 0x35)
Addr. RegName
(Reset val)
Signal name SYNC_MISS_TH
Width Property Description [7:4] [3:0] R/W R/W Sync byte detector's miss threshold Sync byte detector's hit threshold *Note: This value should be greater than 2
0x35
Sync01 (0x33)
SYNC_HIT_TH
SYNC status register (Address: 0x36)
Addr. RegName
(Reset val)
Signal name BYTE_SYNC
Width Property Description [5] [4:1] R R R [1] Acquire byte sync [0] Not acquire byte sync
0x36
Sync02 (0x00) VIT_SYNC
Reserved [1] Viterbi decoder is in sync [0] Viterbi decoder is out of sync
[0]
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S5H1420
DBS Channel Decoder for DVB-S/DSS
MPEG control registers (Address: 0x38~0x39)
Addr. RegName
(Reset val)
Signal name ERR_POL
Width Property Description [3] R/W Packet error polarity [1] Active low [0] Active high Sync polarity [1] Active low [0] Active high Data valid polarity [1] Active low [0] Active high CDCLK polarity [1] Falling edge event [0] Rising edge event [6] [5] [4] R/W R/W R/W R/W R/W R/W Set to "1" Set to "1" Set to "1" Clock continuous mode [1] Continuous clock, [0] Clock is enable during payload data transfer Set to "1" Serial / Parallel mode [1] Serial mode, [0] Parallel mode DSS sync mode [1] Output sync, [0] No output sync
SYNC_POL
[2] [1]
R/W R/W
0x38
Mpeg01 (0x00)
VALID_POL
CDCLK_POL
[0]
R/W
CLK_CONT
[3] [2]
0x39
Mpeg02 (0x3D) SER_PAR
[1]
DSS_SYNC
[0]
R/W
DiSEqC control registers (Address: 0x3A~ 0x3C)
Addr. RegName
(Reset val)
Signal name TONE_FREQ
Width Property Description [7:0] R/W Tone frequency ratio *Note: ftone = fclk / (TONE_FREQ x32)
0x3A
DiS01 (0x01)
RCV_EN DIS_LENGTH
[7] [6:4]
R/W R/W
DiSEqC receive enable mode [1] Receive enable [0] Receive disable Message length Data Transfer ready / finish [1] Ready [0] Finish
DIS_RDY DiS02 (0x00) SWICH_CON
[3]
R/W
0x3B
*Note: The Microprocessor set to "1" only when this bit is "0". When this bit is "1", the slaver is not yet received message. The slaver is starting to receive the signal at the rising edge detection Satellite switch in tone burst mode [1] Satellite B [0] Satellite A LNB control mode [0] Continuous mode
[2]
R/W
LNB_CON
[1:0]
R/W
[1] Tone burst mode [2] DiSEqC mode [3] Reserved
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S5H1420
DBS Channel Decoder for DVB-S/DSS Addr. RegName
(Reset val)
Signal name OLF_N
Width Property Description [2] [1] [0] R/W R/W R/W [1] Disable [0] OLF (active low) [1] LNB down [0] Disable (active high) 13V/18V select register [1] 18V [0] 13V
0x3C
DiS03 (0x04)
LNB_DN 18V_13V
DiSEqC message registers (Address: 0x3D~0x44)
Addr. RegName
(Reset val)
Signal name LNB_MESGE0
Width Property Description [7:0] R/W LNB message contents *MSB sent first on each byte
0x3D
DiS04 (0x00) DiS05 (0x3E) DiS06 (0x00) DiS07 (0x00) DiS08 (0x00) DiS09 (0x00) DiS10 (0x00) DiS11 (0x00)
0x3E 0x3F 0x40 0x41 0x42 0x43 0x44
LNB_MESGE1
[7:0]
R/W
LNB_MESGE2
[7:0]
R/W
LNB_MESGE3
[7:0]
R/W
LNB_MESGE4
[7:0]
R/W
LNB_MESGE5
[7:0]
R/W
LNB_MESGE6
[7:0]
R/W
LNB_MESGE7
[7:0]
R/W
RF slave register (Address: 0x45)
Addr. RegName
(Reset val)
Signal name SLAVE_ADDR
Width Property Description [6:0] R/W RF tuner slave Address (SOC VERSION)
0x45
Rf01 (0x61)
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S5H1420
DBS Channel Decoder for DVB-S/DSS
Error control register (Address: 0x46)
Addr. RegName
(Reset val)
Signal name
Width Property Description [4] [3:2] R/W R/W Set to "1" Set to "1" Error monitoring source
0x46
Err01 (0x00) ERR_SRC [1:0] R/W
[0] QPSK bit errors [1] Viterbi bit errors [2] Viterbi byte errors [3] Packet errors
Error monitoring registers (Address: 0x47-0x49)
Addr. RegName
(Reset val)
Signal name ERR_CNT_L
Width Property Description [7:0] R Error counter value register (LSB 8 bits)
0x47 0x48 0x49
Err02 (0x00) Err03 (0x00) Err04 (0x00)
ERR_CNT_H
[7:0]
R
Error counter value register (MSB 8 bits)
PARITY_ERR
[7:0]
R
Error flag for DiSEqC receive data
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S5H1420
DBS Channel Decoder for DVB-S/DSS
5. ELECTERICAL CHARACTERISTICS
5.1 Absolute maximum ratings Symbol Parameter Range Unit DC Supply Voltage -0.3 to 4.6 V VCC 3.3V Input Voltage -0.3 to VDD+0.3 V VIN DC 3.3V Input Current +/- 10 mA IIN Storage Temperature -40 to +125 C Tstg Operation Temperature 0 to +70 C Topr 5.2 Recommended operating conditions Symbol Parameter Range Unit DC Supply Voltage 3.0 to 3.6 V VCC Junction Temperature MAX 125 C TJ Thermal Resistance 45 C /W TR DC Input 0 to VCC V VIN Output Voltage 0 to VCC VOUT Lead Temperature (soldering 10 sec) 300 C TLT 5.3 DC electrical characteristics (VDD = 3.3+/-10%, Ta = -40(C~ -85(C, unless otherwise specified) Symbol Description Test Condition Min Typ Max Unit VCC33 I/O Supply Voltage 3.0 3.3 3.6 V VCC25 Internal Supply Voltage 2.2 2.5 2.7 V All In out 0.7 Vih Input Voltage Low VDD Rst_n, S_clk 2.1 V All Input 0.3VD V D Vil Input Voltage High Rst_n, S_clk 0.8 Iih High Level Input Current VIN = VDD - 10 + 10 uA Low Level Input Current VIN = VSS -10 +10 uA Iil Output Low Voltage IOL = 8mA 0.4 V Vol Output High Voltage IOH = -6mA 2.4 VDD V Voh 3-State Output Leakage -10 +10 uA VOH = VSS or VDD Ioz Current Fin = 4.0MHz, TBD mA Dynamic Supply Current Icc VDD = 3.6V 5.4 A/D converter (Vcc25 = 2.5+/-5%, Ta = -40(C~ -85(C, unless otherwise specified) Symbol Description Test Condition Min Typ Max Unit VREF-H Reference Voltage High Input VREF-H Value 1.5 1.6 1.7 V VREF-L Reference Voltage Low Input VREF-L Value 0.8 0.9 1.0 V Ain Analog Input (IP/IN/QP/QN) (VREF-H)-(VREF-L) 0.5 0.7 0.9 VPP CML Common Mode Level CML Output 1.25 IDD 45M Average VDD_2.5V Current VDD=2.6V = 59MHz mA IDD 45M Average VDD_2.5V Current VDD=2.6V = 88MHz mA INE Integral Linearity Error FIN=30MHz, FS=90MHz dB 1.0 DLE Differential Linearity Error FIN=30MHz, FS=90MHz dB 2.0 OFF Offset Error Voltage FIN=30MHz, FS=90MHz dB 1.0 GAIN Gain Error Voltage FIN=30MHz, FS=90MHz dB 2.0 Signal to Noise & SNDR -32 -30 -28 dB FIN=30MHz, FS=90MHz Distortion Ratio FIN Analog Input Bandwidth 30 MHz FS Sampling Frequency 90 MHz - 26 Samsung Electronics Co, Ltd. Proprietary Information
S5H1420
DBS Channel Decoder for DVB-S/DSS
5.5 Timing characteristics
Sym bol
f VCO f CLK_IN
Parameter
Internal VCO frequency CLK_IN OR XTAL frequency
Min
300 4
Typ
Max
400 30
Unit
MH z MH z
P A R A L L E L O U T P U T D [7 :0 ], D /P , C L K _O U T , S T R _O U T , E R R O R O U T P U T C H A R A C T E R IT IC S Bit RS=1 in RS CONTROL REGISTER(Address33). R efer to Figure 6 tCLK_duty tCKSU t CKH CLK_OUT duty cycle D[7:0], D/P, STR_OUT, ERROR stable before CLK_OUT Falling Edge D[7:0], D/P, STR_OUT, ERROR stable after CLK_OUT Falling Edge 40 2*Tm (1) 50 60 % ns
2*Tm (1)
ns
Bit RS=0 in RS CONTROL REGISTER(Address33). R efer to Figure 7 tCKSU t CKH D[7:0], D/P, STR_OUT, ERROR stable before CLK_OUT Falling Edge D[7:0], D/P, STR_OUT, ERROR stable after CLK_OUT Falling Edge 2*Tm (1) ns
2*Tm (1)
ns
SER IAL O U T P U T D [ 7 : 0 ] , D / P , C L K _ O U T , S T R _ O U T , E R R O R O U T P U T C H A R A C T E R I T I C S Bit RS=1 in RS CONTROL REGISTER(Address33). f CLK = 90MHz. Refer to Figure 8 tCKSU t CKH D[7:0], D/P, STR_OUT, ERROR stable before CLK_OUT Falling Edge D[7:0], D/P, STR_OUT, ERROR stable after CLK_OUT Falling Edge 3.5 ns
2 f CLK = 90M H z. Refer to Figure 9 3.5
ns
Bit RS=0 in RS CONTROL REGISTER(Address33). tCKSU t CKH D[7:0], D/P, STR_OUT, ERROR stable before CLK_OUT Falling Edge D[7:0], D/P, STR_OUT, ERROR stable after CLK_OUT Falling Edge
ns
2
ns
Figure 6
CLK_OUT D[7:0], D/P STR_OUT, ERROR
Figure 7
CLK_OUT D[7:0], D/P STR_OUT, ERROR
tCKSU
Figure 8
tCKH
Figure 9
tCKSU
tCKH
CLK_OUT D[7:0], D/P STR_OUT, ERROR
CLK_OUT D[7:0], D/P STR_OUT, ERROR
tCKSU
tCKH
tCKSU
tCKH
- 27 Samsung Electronics Co, Ltd. Proprietary Information
S5H1420
DBS Channel Decoder for DVB-S/DSS
5.6 I2C bus characteristics
Symbol VIL VIH VOH VOL ILK CIN IOL fSCLN fSCLS tBUF tHD,STA tLOW tHIGH tSU,STA tSU,STO tSU,DAT tR, tF CB Bus Free Time between a STOP and START Condition Hold Time(repeated)START Condition. After this period, the first clock pulse is generated Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a repeated START Condition Setup Time for STOP Condition Data Setup Time Rise and Fall Time of both SDA and SCL signals Capacitive Load for each Bus Line 400 pF 1.3 0.6 0.6 0.6 100 300 us us us us ns ns 0.6 us Parameter Low Level input Voltage High Level input Voltage High Level output Voltage Low Level output Voltage Input Leakage Current Input Capacitance Output Sink Current SCL Clock Frequency VIN = 0V to 5V 0 VOL = 0.5V Normal Mode Standby Mode 0 0 1.3 -10 3.5 10 fM_CLK /40 fM_CLK /10 Pull up to 5V 10% Test Condition s Min - 0.5 2.0 Typ Max 0.8 5.5 5.5 0.4 10 Unit V V V V uA pF mA _ _ us
Pull up to 5V 10%
I2C bus timing diagram
- 28 Samsung Electronics Co, Ltd. Proprietary Information
S5H1420
DBS Channel Decoder for DVB-S/DSS
6. APPLICATION EXAMPLES # Application example (with DVB-S I/Q Tuner)
AVDD_ADC
AVBB_ADC
AVSS_ADC
AVSS_ADC 49 48
BYTE_CLK
LNB_EN
VREF_H
VREF_L
DiSEqC
VDD25
VSS25
VSEL
AGC
CML
DATA 7
OLF RESET_N ERROR SYNC VALID
QN 50
QP 51
TEST_SEL0
TEST_SEL1
AVDD_PLL
AVSS_PLL
CLK_SEL
ID_SEL0
ID_SEL1
DATA6
DATA7
VDD25
VDD25
VSS25
VSS25
SDA
SCL
NC
SMPS LNBP
MPEG2 Serial Interface MPEG2 Parallel Interface
64 63 62 61 60 59 58 57 56 55 54 53 52 IN IP AVDD_ADC ADC_OSC_IN VDD25 VSS25 RFSCL RFSDA VDD33 VSS33 FMHZCLKOUT XTAL_OUT XTAL_IN AVSS_PLL AVDD_PLL AVBB_PLL 1 2 3 4 5 47 46 45 44
S5H1420
(64LQFP-1010)
43
NC VSS25D VDD25D DATA0 DATA1 DATA2 DATA3 VSS33 VDD33 DATA4 DATA5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
42 41 40 39 38 37 36 35 34 33
Samsung Electronics Co, Ltd. Proprietary Information
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S5H1420
DBS Channel Decoder for DVB-S/DSS
7. Package Dimension
12.00 + 0.20
10.00
0-7
0.127
+ 0.073 - 0.037
0.25TYP
+ 0.20
10.00
12.00
0.08 MAX
#64
#1
0.50
0.20
+ 0.07 - 0.03
0.08 MAX
M
NOTE: Dimensions are in millimeters.
0.45 - 0.75
0.05 MIN
1.40 + 0.05
1.60 MAX
- 30 Samsung Electronics Co, Ltd. Proprietary Information
S5H1420
DBS Channel Decoder for DVB-S/DSS
8. Data sheet update history - 2004-01-05 : Release version : 4.5
Add chapter : 3.4.8 Spectrum Inverse of Code Rate 5/6 (Page 10). Add chapter : 3.4.9.3 MPEG Clock Control (Page 12). Change register map : (Page 16).
- 2004-01-10 : Release version : 4.5.1 Update chapter : 3.2.2 Loop equation (Page 7). Update chapter : 3.3.1 Loop equation (Page 7). Update chapter : 3.4.9.2 Serial output interface (Page 10). Update chapter : 3.4.9.3 MPEG Clock Control (Page 12).
Samsung Electronics Co, Ltd. www.samsung.com T : 82-31-279-7640 Suwon P.O.BOX 416 Maetan-3dong, YoungTong-gu, Suwon-si, Gyeonggi-do, Korea 442-742
- 31 Samsung Electronics Co, Ltd. Proprietary Information

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